• GIC v3&4: Programming sequence of GIC Registers
    Hi., Is there any sequence in programming GIC Registers. Physical Interrupts point of view, I have followed sequence as follows: GICD GICR GICC/ICC Coming to Virtual Interrupts point of view, I had small...
  • GIC virtualization -- GICH_ELRSR and hardware interrupts
    Consider a hypervisor injecting a hardware interrupt in a virtual machine, by setting the HW bit in a List Register (LR). According to the GICv{2,3,4} specification, after the virtual machine has taken...
  • GIC-400 non-secure access
    Hi, experts I'm the new one porting armv8 linux. I have some problem about gic400 access. In the porting linux progress,CPU will switch to EL1NS. In gic_dist_init() function, I read the the  GICD_ISENABLERn...
  • The non-secure copy of the GICC_CTLR gives FIQEn bit as reserved. How to configure GIC to generate FIQ in this case?
    In the the arm gic arch specification  (version 2) section 3.9.2,   it has been given that for any implementation of GICv2 (with or without Security Extn) we can configure the GIC to generate FIQ for...
  • why the inter-core SGI interrupt cannot be trigged on GICv3 hardware
    My hareware environment: 1.  a ARMv8 processor , which  runs in 64bit EL3 and 32bit EL2&EL1. 2. a GICv3 interrupt controller Running in 32bit hyp mode,  I try to send a SGI interrupt from core0 to core1...