• Cortex A9 dual core - How to achieve an AMP system without an RTOS?
    One of my customer is considering to use Cortex A9 dual core device for a computational intensive task (For the sake of discussion, lets assume an high end image analysis task). Due to cost or other over...
  • AMP Baremetal on SoC using Terasic DE1-SoC Computer system?
    I have a Terasic DE1-SoC with the implimented Computer system. Can someone give me a step by step process to run two separate binaries on both A9 cores using baremetal with AMP configuration? One processor...
  • TCP/IP stack for Cortex-A9 MPCore
    Hi, I'm currently working on a project based on the Arria V SoC FPGA (ARM Cortex-A9 MPCore). The goal of this project is to run a high speed ethernet link. For some reasons the customer don't want to...
  • Anyone knows of any Cortex-A9 development boards?
    We've been using TI's Panda board but it seems to give us quite a bit of trouble.  As a result we can't profile the information that we would like.  Does anyone know of any other development boards out...
  • Converting virtual address of Instruction fault address register to physical address in cotex A9
    Content of IFAR=0xaa4e8ef0 IFSR=0x0000000d DFSR:0x00000000 DFAR:0x00004000 How to find Physical address form this?