• outsanading behaviour in AXI Vs memory latency
    I am trying to implement the axi outstanding feature in CPP, i tried to search if there is already a model in CPP, did not find alot. Is there such model ? If not, Is there any diff in terms of READ and...
  • Introduction to AXI Protocol: Understanding the AXI interface
    When part of a team, your group can become more capable than a single individual, but only if your team can work together and communicate effectively. Having members of a group talk over each other leads...
  • Write Data Interleaving - AXI
    Note: This was originally posted on 19th March 2009 at http://forums.arm.com Hello, Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec...
  • AXI Read/Write ordering
    Note: This was originally posted on 24th October 2007 at http://forums.arm.com Hello,    Section 8.6 of the AXI spec says that reads and writes have no ordering restrictions between them.  It then says...
  • AXI write strobes
    Note: This was originally posted on 21st February 2007 at http://forums.arm.com the AXI spec says: 10.1 About unaligned transfers [...] For any burst that is made up of data transfers wider than one byte...