• AXI3 write data interleaving with same AWID
    This is regarding the AXI3 write data interleaving. I understand how the write data interleaving works when AWID=WID when a slave is accessed by multi masters or a single master which can generate multiple...
  • AXI
    What is byte lane in AXI?
  • AXI
    Why burst must not cross 4kb in AXI ?
  • AMBA AXI reset
    According to spec IHI0022D_amba_axi_protocol_spec section A2.1 page number: A2-28 "All signals are sampled on the rising edge of the global clock " Q) Should RESET_N also be sampled on the rising...
  • Transfer size in AMBA AXI
    Hi, I am not so clear about the concept of transfer size in AMBA AXI. My question is how to calculate wrap_boundary in wrap based data transfer when Number_Bytes (The maximum number of bytes in each data...