• Weird SPSR behaviour
    I was trying to write a register context saving/restoring when I came across a weird behaviour. My code (sorry, tried to format tens of times, but the editor WANTS to make asm a table): asm volatile ...
  • How to access the memory mapped debug registers?
    Now that the funny PABT-behaviour is found to be (probably) caused ny debug state, I'd like to exit debug state before return from PABT exception. The ARM v7-A/R ARM says that I should write RRQ to DBGDRCR...
  • Issue in writing a data in PMU register
    Hi, Following are the query regarding the ARM Cortex A7 MP Core. In ARM Cortex A7 MP Core,facing a issue in memory mapping the registers and accessing the registers by read and write operations. By means...
  • What's wrong when watchpoint doesn't watch?
    I've been trying to get a watchpoint to trigger, but no luck. There should be 4 watchpoints accordíng to DBGDIDR, DBGDSCR=0x0204000e, so there shouldn't be any problems there? I use (just in case) the...
  • ARM instruction set pseudo instructions
    Does anyone know if there is a list of ARM instruction set pseudo instructions? Or better yet, an instruction list like PPC's, where there is a list of 'true instructions' with mnemonics and another list...