• AXI
    What is byte lane in AXI?
  • AXI
    Why burst must not cross 4kb in AXI ?
  • AXI protocol
    Note: This was originally posted on 30th December 2007 at http://forums.arm.com Can anyone tell me the exact explanation and differnce between out of order completion and write data interleaving  in detail...
  • AXI transaction
    Axi master initiating the incr transfer of length let's say 15 means there is total 15 write transfer are there of 4 byte on 32 bit data bus. So now does AXI slave update the memory just after getting...
  • AXI transfer
    Consider Data interface is 64 bit. It is Write transfer. AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios. Scenario...