• Burst Length of wrap type in AXI4
    As per spec, the burst length of wrap type should be 2,4,8 or 16. But at the same time it is also mentioned that burst length= AxLEN[7:0] +1, to accommodate the extended burst length of the INCR burst...
  • AXI3 write response dependencies
    Write Transaction dependencies define that WVALID and WREADY, both are asserted then BVALID can be asserted. So the issue can be raised there that what if AWVALID and AWREADY, both are deasserted (means...
  • AMBA AXI Write response
    I am just going through the specs of AMBA AXI. I've few questions.It will be great if anybody clarify 1) Why there was no Write response for each beat in burst Write. But there is a seperate Read response...
  • AXI read response in error case
    Hi, In the AXI spec it is mentioned that , even in case of ERROR response, the slave needs to respond with the exact number of beats and indicate the response with each beat. Now my question here...
  • outsanading behaviour in AXI Vs memory latency
    I am trying to implement the axi outstanding feature in CPP, i tried to search if there is already a model in CPP, did not find alot. Is there such model ? If not, Is there any diff in terms of READ and...