• AXI3 write data interleaving with same AWID
    This is regarding the AXI3 write data interleaving. I understand how the write data interleaving works when AWID=WID when a slave is accessed by multi masters or a single master which can generate multiple...
  • AXI3 locked access
    I want to know what happens in these scenarios : 1) Assume Master1 (M1) is doing locked access, if locked access fails before M1 does unlocking transaction what is the response to the M1? 2) Assume M1...
  • AXI3 write response dependencies
    Write Transaction dependencies define that WVALID and WREADY, both are asserted then BVALID can be asserted. So the issue can be raised there that what if AWVALID and AWREADY, both are deasserted (means...
  • Sampling on positive edge of clock of slave in AXI3
    How do you confirm if a slave is sampling on positive edge of clock only ? How can we prove this in simulation
  • pseudocode description of transfer in AXI
    Hello I am new to AXI and just saw the pseudocode for a transfer in the spec of AXI . My question is regarding Data_Bus_Bytes . Q1- The spec says that Data_Bus_Bytes is number of 8 bit byte lanes in...