• AXI
    What is byte lane in AXI?
  • AXI
    Why burst must not cross 4kb in AXI ?
  • AXI transfer
    Consider Data interface is 64 bit. It is Write transfer. AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios. Scenario...
  • Write Data Interleaving - AXI
    Note: This was originally posted on 19th March 2009 at http://forums.arm.com Hello, Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec...
  • axi read transfers
    what is the difference between overlapping and out of order transfers in Aciform the explanation it seems that both are same is this the case?