• Cache in SOCs
    Dear Sir/Ma'am, In SOC size of interconnections between multiple processors is very small. So is it possible to have one big size central cache for all processors ignoring access time. I know processors...
  • Cache Maintenance Transactions
    Hi, I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be...
  • AMBA AXI CACHE
    i am not able to understand working of this CACHE signal pleas explain with simple example. thank you!
  • Store operations where the cache line is already cached (ACE protocol)
    In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under " Store operations where the cache line is already cache d" as : The initiating master component...
  • CHI protocol cache line states
    The CHI protocol spec mentions 2 additional cache line states as compared to AXI viz., Unique Clean Empty and Unique Dirty Partial. What is the reason for introducing two additional cache line states...