• AXI transaction
    Axi master initiating the incr transfer of length let's say 15 means there is total 15 write transfer are there of 4 byte on 32 bit data bus. So now does AXI slave update the memory just after getting...
  • burst-based transactions on AXI
    Hi, I'm confusing with burst transaction in AXI. there is one key feature in AXI spec.... > "burst-based transactions with only start address issued" How can we understand this point? ...
  • AXI transaction failure
    Hello everyone, I'm pretty new to axi and i still try to figure things out. I'm using Zybo device and created a custom ip with a master and a slave interfaces. I have create design as you can see in...
  • Problems about signal dependencies in AXI spec
    Hi, In AXI4/5 spec (IHI0022F), it listed a set of signal dependencies for read and write transactions. My problem is in Figure A3-7 AXI4 and AXI5 write transaction handshake dependencies. It noted...
  • RE: In read or write transaction in AXI.what happen if data transaction  is before address.
    Hii, In AXI 3 if data items are written before the address comes due to register delays .....then where that data is being stored in memory because no address is being specified till now...? please...