• Data during AHB Busy state
    Hi everyone, I have a question regarding the data during the BUSY state in a AHB bus. Consider the following example of an AHB master writing data onto an AHB slave: TIME: T1 T2 T3 T4...
  • AHB Busy states...
    Note: This was originally posted on 24th November 2008 at http://forums.arm.com Hello guys.... If master is doing transfer of fixed length burst and last address is driven on bus... Can master drive htrans...
  • AHB wait state insertion
    1.In AHB except a single transfer inset a wait state in middle of the burst only or insert anywhere in a burst. 2. In INCR burst transfer can i insert a BUSY in a middle of the burst or must insert...
  • Burst termination with BUSY transfer on AHB
    I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated. But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length...
  • AHB amba 5 lite - waited write transfer
    Hello, i didnt find at spec any note about the waited write transfer. for example T1 : NONSEQ + write transfer + HREADY is high T2: HREADY dropped + HTRANS is idle - HWDATA ? does the HWDATA...