• GICv2 deactivation feature.
    Hello all, There is one thing which is unclear for me in GICv2. GICv3 spec. explicitly says "SGIs and PPIs must be deactivated by the PE that activated the interrupt. SPIs can be deactivated by a...
  • GICv2's programming errors -- several LRs with same SGI but distinct CPUIDs
    The GICv2's documentation describes as a programming error (see 5.2.4) having two or more copies of the same interrupt in the List registers . The notion of "same interrupt" is a bit vague when it comes...
  • GICv2 How to resolve Multiple Interrupt appearing on a CPU
    Hi All, I am facing issue where, in the event of multiple interrupts on GIC in close vicinity, I am unable to decide on which interrupt has been asserted, to service them properly. Details:- This...
  • why the inter-core SGI interrupt cannot be trigged on GICv3 hardware
    My hareware environment: 1.  a ARMv8 processor , which  runs in 64bit EL3 and 32bit EL2&EL1. 2. a GICv3 interrupt controller Running in 32bit hyp mode,  I try to send a SGI interrupt from core0 to core1...
  • GICv3 -- accessing the redistributors of other cores
    In GICv2, per-core interrupts (SGIs and PPIs) are configured through banked registers in the distributor, which means that a core cannot access the configuration of the SGIs and PPIs of the other cores...