• How to access the memory mapped debug registers?
    Now that the funny PABT-behaviour is found to be (probably) caused ny debug state, I'd like to exit debug state before return from PABT exception. The ARM v7-A/R ARM says that I should write RRQ to DBGDRCR...
  • Weird SPSR behaviour
    I was trying to write a register context saving/restoring when I came across a weird behaviour. My code (sorry, tried to format tens of times, but the editor WANTS to make asm a table): asm volatile ...
  • Basic register write data changes in assembly when NOP added
    Hi all, I am doing a basic register read/write on a custom SoC with ARM Cortex A53 and many other peripherals added with an AXI fabric integrated. Using the below code in assembly after bringing up...
  • Write Data Interleaving - AXI
    Note: This was originally posted on 19th March 2009 at http://forums.arm.com Hello, Can anybody help me to understand the reasoning behind write data interleaving ordering restriction imposed by AXI spec...
  • Handshaking for the write data channel
    i am writing a verification code for handshaking. i want to assert the WVALIDin same ACLK cycle where the WVALIDis deasserted due to detecting the corresponding WREADY from the slave. please give me...