• How to handle clean operation in Data Cache
    Hi, I have a question. when a processor sends a clean request to data cache, how data cache should behave? 1. does it need to evict all cache lines present in cache (including clean lines) or does...
  • ACE5 / ACE5 Lite questions for ARBAR/AWBAR, AWSTASH*, and BROADCAST* signals
    Hi, 1) ARBAR/AWBAR These two signals are mentioned : ARBAR, AWBAR but in the AMBA5 spec F2.1 Signal Matrix, these signals are listed as "N" (must not be present), page 419 and 420 of 440 pages. ...
  • Exploring the ARM CoreLink CCI-500 performance envelope - Part 1
    Introduction You may have noticed the ARM announcement last week of a group of Premium Mobile products (if not you can find it here ARM Sets New Standard for the Premium Mobile Experience - ARM )...
  • AHB Lite
    Hi All, In the AHB Lite protocol, if slave provides error response then to terminate the current burst can master perform NON SEQ transfer to start another burst or it needs to first perform IDLE transfer...
  • ACE-Lite
    Hi, Can we develop the VIP of ace-lite without developing the ace. Like for ace-lite VIP development instead of taking two ace masters and one ace-lite master can we take only three ace-lite masters...