• Questions about Barrier instructions & ACE Barrier transactions
    1. How barrier instructions like `dmb ishld` and `ldar/stlr` translate to ACE barrier transactions? I am curious about how barrier instructions which will only affect specific types of memory operations...
  • Barrier Transactions in ACE
    Can somebody please explain how barrier transactions in ACE work? Thanks in advance.
  • Cache Maintenance Transactions
    Hi, I am reading ACE protocol and i am confused about when to use cache maintenance transactions. On what basis should i decide when to use cache maintenance transaction and which transaction to be...
  • Axi4 Write Transaction
    I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.
  • What kind of memory barrier should be followed by writes ICC_SGI1R_EL1?
    As we all know, ICC_SGI1R_EL1 is used to produce another core's interrupt. I am a software engineer. My question is what kind of memory barrier should be followed by writes ICC_SGI1R_EL1? This question...