• AXI4 Burst Transactions
    I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction. Eg. Burst length- Two , Burst size 16 bytes. Please give me answers...
  • AXI Burst Size meaning
    Dear Community, I am reading AXI speck from the ARM, please help better understand the AXI, by answering my questions regarding to Burst transaction. a) I cannot clearly understand the meaning of Burst...
  • AXI transaction failure
    Hello everyone, I'm pretty new to axi and i still try to figure things out. I'm using Zybo device and created a custom ip with a master and a slave interfaces. I have create design as you can see in...
  • AXI transaction
    Axi master initiating the incr transfer of length let's say 15 means there is total 15 write transfer are there of 4 byte on 32 bit data bus. So now does AXI slave update the memory just after getting...
  • AXI fixed burst to a slave with narrow data width
    Hi, I have an AXI master with data width 64, and an AHB slave of data width 32. What would happen when there is a 64bit FIXED burst READ (i.e., asize=3 )to an address 0X100 of the slave? Would the...