Burst termination with BUSY transfer on AHB

I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated. But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length...
AHB Lite Multiple burst without idle transfer

Hi All, Consider the following burst transfers. 1. INCR4 (WR) IDLE INCR4(RD) 2. INCR4 (WR) INCR4(RD) 3. INCR4 (WR - WR1 ,WR2, IDLE, WR3 ,WR4 ) INCR4(RD) All the above transactions are valid...
AHB master continues transfer after error response

Hi Everyone, Consider an AHB transaction in which the AHB slave signals an error response, and the AHB master decides to continue the transfer with the present slave. Following are three waveforms that...
AHB WRAP4 transfer

Hi sir, I am now new to AHB. In the AHB wrap4 transfer, i can use a second cycle is a busy cycle, and also i am using a WAIT state for first 4 clock .In spec says if u use a busy state then the slave...
AHB Busy states...

Note: This was originally posted on 24th November 2008 at http://forums.arm.com Hello guys.... If master is doing transfer of fixed length burst and last address is driven on bus... Can master drive htrans...