• AHB Busy states...
    Note: This was originally posted on 24th November 2008 at http://forums.arm.com Hello guys.... If master is doing transfer of fixed length burst and last address is driven on bus... Can master drive htrans...
  • Burst termination with BUSY transfer on AHB
    I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated. But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length...
  • BUSY transfer and WAIT state both are using the same time ,How to perform the AHB?
    Hi sir, T1=NON-SEQ T2=BUSY T3=SEQ T4=SEQ T5= SEQ This is for WRITE operation: i am using a BUSY state for T2. Then my WAIT state for till T3. I have read from the forum if WAIT state u are...
  • AHB wait state insertion
    1.In AHB except a single transfer inset a wait state in middle of the burst only or insert anywhere in a burst. 2. In INCR burst transfer can i insert a BUSY in a middle of the burst or must insert...
  • State Machine for AHB-Lite Protocol
    This is more of a conceptual doubt than a doubt in protocol. I've come across many papers where state machines are designed for AHB and AHB-Lite. I never understood why a state machine is required and...