Cache in SOCs

Dear Sir/Ma'am, In SOC size of interconnections between multiple processors is very small. So is it possible to have one big size central cache for all processors ignoring access time. I know processors...
Designing a Multimedia SoC using system-level simulation

This video demonstrates the use of system-level architecture exploration for sizing and hardware-software partitioning. This is an example of the performance modeling using a set of standard IP blocks...
CPUIdle Marvell SoC

Hello, I'm facing an issue with some of the linux kernel code. I'm trying to use the CPU suspend fonction (located in arch/arm/kernel/sleep.s) of the linux next kernel The code is the following: ...
Import SOC design in eclipse

I have design SOC in system canvas . its build successfully on ISIM and cadi target but when I import in DS Eclipse it shows error I am adding.exe file
AMP system on Cortex-A9. How to do it?

Hello everyone. I'm trying to understand how to create and make work two separate baremetal programms on two cores of cortex-a9. I'm using Cyclone V SoC. DS-5, arm compiller 5, DE1-SoC board by terasic...