Burst termination with BUSY transfer on AHB

I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated. But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length...
AHB frequency

Note: This was originally posted on 6th January 2009 at http://forums.arm.com Hi Friends, My doubt is : what is the maximum AHB clock frequency ? Regards, P.Vignesh Prabhu
AHB Arbiter

Note: This was originally posted on 21st November 2008 at http://forums.arm.com Y is it necessary to provide HADDR input to the arbiter in AHB bus protocol ?
AHB Multilayer

Note: This was originally posted on 30th April 2008 at http://forums.arm.com In the multilayer environment, i found a interconnect matrix with interface signals on the Master side having a hsel signal...
AHB WRAP4 transfer

Hi sir, I am now new to AHB. In the AHB wrap4 transfer, i can use a second cycle is a busy cycle, and also i am using a WAIT state for first 4 clock .In spec says if u use a busy state then the slave...