• AMBA 5 CHI Memory Attributes
    CHI-B Spec Page number 2-93 states that writes must not be merged in the device memory type description. I am unable to understand: a) What is this merging? b) How to merge different writes? Also...
  • Error in AMBA 5 CHI spec?
    P189, 5.2.1 Dataless transaction without memory update Why does RN-F0 transition I->UC, rather than UCE or UD? After MakeUnique, RN-F0 has obtained the right to modify the cache line by discarding all...
  • ARM CHI Issue C Specification - Can we receive DataSepResp, RespSepData in any order at a CHI Requester Node?
    Can we receive RespSepData, DataSepResp in any order at a CHI Requester Node? and if a DataSepResp is received before RespSepData will it be considered as a valid Response of the Request, Should the Request...
  • AMBA 5 CHI Link Layer (L-Credit Return)
    Is it possible for a CHI Node to receive an L-Credit Return when in RUN State?
  • CHI protocol cache line states
    The CHI protocol spec mentions 2 additional cache line states as compared to AXI viz., Unique Clean Empty and Unique Dirty Partial. What is the reason for introducing two additional cache line states...