• GIC500 :: Not able to disable Affinity Routing
    I'm not able to disable the affinity routing (i.e. ARE_S and ARE_NS bits being set always). Reset value of GICD_CTLR register is 0x30. Actually I want to forward the interrupt from Distributor to multiple...
  • GIC 3.0's SGI interrupt latency seems much bigger than GIC 2.0
    Hi, I tested SGI interrupt latency, it seems that GIC3.0's SGI interrupt latency are much bigger than GIC2.0. How to test: GIC3.0: 1. read timestamp(t01) 2. core0 write ICC_SGI0R_EL1 to trigger...
  • GIC500 :: How to forward interrupts to multiple cores using GICD_IROUTER
    Is there a way to forward the interrupts from Descriptor to multiple Cores using GICD_IROUTER ? Seems the Affinity Routing field in my case is hard-tied to 1. P.S. The SoC I'm working on, do have...
  • What kind of memory barrier should be followed by writes ICC_SGI1R_EL1?
    As we all know, ICC_SGI1R_EL1 is used to produce another core's interrupt. I am a software engineer. My question is what kind of memory barrier should be followed by writes ICC_SGI1R_EL1? This question...
  • GIC v3&4: Programming sequence of GIC Registers
    Hi., Is there any sequence in programming GIC Registers. Physical Interrupts point of view, I have followed sequence as follows: GICD GICR GICC/ICC Coming to Virtual Interrupts point of view, I had small...