• AXI4 Burst Transactions
    I am new to AXI4 protocol. I would like to know how many clock cycles are required to complete a AXI4 burst write transaction. Eg. Burst length- Two , Burst size 16 bytes. Please give me answers...
  • AXI4 - read data interleaving
    Hi Folks, We need a clarification on Read Data Interleaving on AXI4 Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving: Multiple Read commands can be executed...
  • Removal of WID's in AMBA AXI4
    Hi , What is the purpose of removing ID's (WID) in AXI4 ? If it because of reduction of pin count then We lost the " Write Data Interleaving" and "Out Of Order " Transaction features. Can you please...
  • Why AXI4 changed the definition of AxCACHE?
    Hi, In AXI4, spec changed the definition of the definition of AxCACHE[3:2] from Write Allocate/Read Allocate to be Allocate/Other Allocate. But is there any concrete reason for this change? Actually...
  • Axi4 Write Transaction
    I got a doubt,Does Master should wait for Bresp to send next Write transaction or it can continuously send the transaction independent for Bresp.