• AXI interconnect performance improvement
    Hi all, I am working on a SOC using Xilinx ZYNQ US+ FPGAs. I am transferring data to DDR4 memory by AXI interconnect cores. I am going to find a way to improve the performance of my interconnect. I...
  • Are CMSIS drivers for Flash portable on all Cortex M0(vendor independent)?
    I am writing open source easy to use top level Flash drivers which are portable to use on all Cortex M0 devices (vendor independent). So I was thinking of using CMSIS flash drivers as my low level block...
  • ARM and Mentor Partnership Improves SoC Test
    During the ARM® -Mentor® seminar Tuesday, July 17, the nearly 100 attendees heard about the goals and ambitions of the long-term partnership between Mentor and ARM to improve testing of ARM cores and...
  • spi flash 16MB not working
    Hi I am currently working with SPI flash memory W25Q128BV and using nuvoton processor of N9H30 series. I have sample codes but not working correctly, but after erse only one time working properly...
  • Handling invalid AXI address requests
    I'm working with the Cortex-M on digilent ARTY FPGA platform. I'm wondering how handling invalid address requests happen on a typical system. I'm guessing the address decoder in the AXI crossbar interconnect...