• How to invalidate cache (NVIDIA Drive PX2, ARMv8)
    Hey, on our development board we use PCIe to exchange data between the two Tegras on a NVIDIA Drive PX2 . Basically the data coming across NT ports acts like a DMA engine writing to system RAM. With...
  • How to handle Cache flush in ACE?
    Hi, I want to know which transaction should be issued by ACE interface on the channel when a flush/clean request is being processed by the cache? Can anyone please help. Regards, Taniya...
  • Store operations where the cache line is already cached (ACE protocol)
    In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under " Store operations where the cache line is already cache d" as : The initiating master component...
  • Instruction and data cache dump from a-53
    Hi ARM experts, Before posting , i went through http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500d/DDI0500D_cortex_a53_r0p2_trm.pdf 6.7: - Direct access to internal memory c0 ...
  • Instruction and data cache dump from a-53
    Hi ARM experts, Before posting , i went through http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500d/DDI0500D_cortex_a53_r0p2_trm.pdf 6.7: - Direct access to internal memory c0 ...