• Cortex-M MPU limitations
    Hi All, The title may seem a bit negative, just from my personal point of view. What is the main reason of the two requirements of setting up MPU, namely size and start addresses of MPU regions. First...
  • Understanding XDMAC on Cortex-M7
    I've inherited some XDMAC code and no one that wrote this code really seems to be able to explain anomalies that I am seeing. So, I'm trying to understand just the basics in an attempt to make sure it...
  • MIPS of Arm cortex m7
    Hi. I need the MIPS of cortex m7 processor. The results which I saw on wikipedia were in DMIPS. But i need it in MIPS only. Can someone help me with it? Thanks, Shreyas
  • Cortex-M7 VFMA usage
    Dear All, this is my first post and I hope I do not make any serious mistakes. My question is regarding the use case of the cortex-m7 VFMA/VMLA instruction. I am evaluating a polinomial for which...
  • Cortex M7 irq enable/disable
    In the appnote "ARM Cortex-M Programming Guide to Memory Barrier Instructions" there is a section that describes the use of memory barriers in the Cortex-M processors on a case-by-case basis. Are those...