• instructions fetch
    Hello, when I use stm32f103xx, I am confused of one of the boot modes it supported. One of the boot modes is booting from embedded SRAM while the I-BUS of Cortex-M3 is connected to FLASH only . When boots...
  • If the mispredict happen, is there a mechanism to abort the instructions(have been fetched or decoded)?
    If the mispredict happen, is there a mechanism to abort the instructions(have been fetched or decoded)? If there is the mechanism, how does it work? Thanks very much!
  • What happens to the Instructions already in pipeline when interrupt occurs ?
    Hello Community, Recently I was going through some code and has this doubt. My Pseudocode ============ CPSID I - Disable interrupts Do critical work CPSIE I - Enable interrupts Do non critical...
  • Disabling PFU / instruction pre-fetch on Cortex-R4?
    Hello, I'm trying to find the proper way to disable PFU / instruction pre-fetch on an R4. System control register bit 12 might do the job, but it's not clear to me: Determines if instructions can...
  • Cortex-A8 : instruction fetch for dual-issue
    Hi, We experiment the following loop code (runs 4096 iterations) and we get CPI=0.66 (in other words, loop initiation interval (II) is about 6 machine cycles). We are trying really hard  to reason why...