• LDREX/STREX on the M3,M4,M7
    Doing some research of the LDREX and STREX it appears that the exclusivity address range for these instructions on the M3,M4,M7 is the entire memory space. Hence you can only use the LDREX/STREX with...
  • STREX always clears the exclusive access tag
    Hello everybody, Section 18.8 Exclusive access of Cortex-A Series Programmer's Guide says the following: STREX can be considered as a conditional store. The store is performed only if the physical address...
  • What is better as mutex on Cortex-M4 - Bitband or LDREX/STREX
    The two options are available. What is the difference in respect of "cost" "speed" and "complexity" for the two method? When we need more than few mutexs like that, say 100, is the answer different?
  • About unsupported exclusive or atomic access issue
    Hi, I am working on TI platform having 2 clusters of Cortex-A53 with 2 cores in each cluster. I am running TI provided Linux on cluster-0/core-0 with HYP mode software controlling stage-2 translation...
  • Does load/store-exclusive violate Hypervisor Transparency?
    Hello Community, I am currently learning hypervisor design using ARM's virtualization extensions (on both ARMv7 and ARMv8). A note in the ARMv8-A reference manual (section D1.5) mentions: "In some systems...