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    In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems...
  • Cortex-A15MP Core Registers
    Hi, I am using ARM v7-A (Cortex A15 MP) and i want to observe the stack context, as i understand it, there are some offset values inside of ARM Core Registers (between LP, SP and PC), and the offset...
  • Is there primask core register in cortex-R5
    Is there primask core register in cortex-R5
  • As arm cortex R4 is a dual core processor, is there a concept of booting core (primary core) and secondary core?
    Cortex R4 processor architecture mentions the processor as dual core. Is there a concept of booting core(primary core) and secondary core? Please provide details on this aspect.
  • Cortex-m0 instructions and core registers immediete values
    Hi, i have just got a cortex-m0(LPC1114) based dev board. I'm reading about the architecture and instructions. My understanding is that it supports most thumb 16-bit instructions and a handful thumb-2...