• Cortex-A35 cache partitioning
    Hi, I am using a Cortex-A35 (Armv8-A) in a processor and I am looking for any technique that could allow the L2 unified cache to support partitioning between running processes (for non interference...
  • System wide cache flush
    Hello, I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system: My need is to flush a cached memory area to RAM in order to be viewed by the M4 core...
  • Cortex M7 cache ECC error
    Hi, I'm currently working on STM32H7 which run a cortex M7. I'm trying to figure out how an ECC error upon a look up in the instruction or data cache is reported to the core. The only mention I've...
  • Guidelines on reducing Cache Miss rate
    Hi Experts, Is there any document on general software guidelines in reducing the cache miss rate in the system for ARMV7 architectures ? If it is more specific to A/R/M then its great..
  • Cortex M7 D cache activated without MPU been enabled
    Hi, I have question related to cortex M7 cache behavior. I noticed that whenever the MPU is disabled after power on reset then I activate data cache I get a hardfault (data cache is already invalidated...