• Allocating memory from heap from within a ISR on Cortex
    Is there is recommandations, hints on do-do-not-do when ISR requires to allocate dynamic memory?
  • Cotex-M7 : Is there any hang case which TCMwait could make?
    Hello, I am using Cortex-M7 Processor and long latency memory with ITCM and DTCM I knew that TCM protocol defines multi-cycles TCMWAIT signal (I read Cortex-M7 TRM). So, I implemented ITCMWAIT and...
  • Shortest code for memory to memory transfer
    Note: This was originally posted on 16th March 2009 at http://forums.arm.com Hi All,     Can anyone tell me what is the shortest code I can use for cortex M3 to transfer (a few words) from one memory...
  • Memory access ordering part 3: Memory access ordering in the Arm Architecture
    In my previous posts, I have introduced the concept of memory access ordering and discussed barriers and their implementation in the Linux kernel . I chose to do it in this order because I wanted to...