• Hard Faults and MemManage Faults in Cortex m3/m4
    I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated....
  • Hard Fault on Cortex M0
    I am using a nRF51422 from Nordic Semiconductor with has an ARM Cortex M0 CPU. While trying to use their Bluetooth Mesh SDK I get a Hard Fault. I am trying to debug the example code to figure out...
  • INVPC Hard fault exception error
    Note: This was originally posted on 16th July 2009 at http://forums.arm.com Using and Arm Cortex M3, the application that is running sometimes will generate a hard fault and deciphering the CFSR register...
  • Hard Fault in cortex m4
    Hello All, Good Morning! I am working on Cortex m4. I have read following about hard fault , "Bus Fault: detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and...
  • hard fault with Cortex M1
    Note: This was originally posted on 24th December 2008 at http://forums.arm.com Hi all, I am developing firmware on Cortex M1 on Actel fusion FPGA.I have built the design that has sram at 0x0 location...