• WFE/WFI and pending interrupts?
    I'd like to know the behavior of WFE and WFI regarding pending interrupts that occur prior to these instructions, on 2 different Cortex profiles.  In both cases, t he goal is to ensure any incoming interrupt...
  • Pending interrupt status
    Hello, If there is a pending interrupt status already set, but it is not being handeled yet, is it possible that somehow that interrupt will no longer have pending status (pending status will disappear...
  • Raising priority of PendSV within NVIC when PendSV pending
    Hi, I'm trying to understand the behavior of raising (lowering numerical priority) the priority of PendSV in the NVIC of a Cortex M4 or M7 when PendSV is already pending. Below are the cases I'm grappling...
  • My application seems to be dropping interrupts; does returning from an interrupt clear its pending flag?
    I'm working with a Cortex M4 (Freescale's Freedom-K64F dev-board). I'm trying to write a long sequence of data to flash. The state machine for this sequence operates in the interrupt handler. This means...
  • A72 not handling IRQ properly
    I want a register write to happen whenever there is an interrupt at irq pin of core 0 and I have written the code for the same. A72 branches to address 0x18 (V=0 and VE=0) by default whenever there is...