• CAT Cache Allocation Technology) and CDP (code and Data Prioritization) features support
    Hi, XEN 4.7 (last version of Hypervisor Xen) is supporting following cache features:   - CAT Cache Allocation Technology   - CDP Code and Data Prioritization Those features are supported by x86 L3 caches...
  • ARMv7 CortexA9 Cache Policy - No allocate ?
    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A...
  • L2 cache with cortex-A8
    Hello, Can I assume that with cortex A8 cache invalidate/flush is used only with L1 ? I have some 2 implementation of this routines, one is called L1 and the other L2C-310. I am just not sure if using...
  • Cache maintanance operation to PoC
    Hi experts, I'm quite confused about cache maintanance operation to PoC on Cortex-A9 (with PL310 L2 cache controller). I'm refererring to the following operations: - DCIMVAC, invalidate data cache by...
  • Cortex-A8 Pipelined cache maintenance
    Hi, I am new to the Cortex-A8, I would like to know what is the advantages of using "pipelined cache maintenance operations". "Auxiliary Control Register " has the "Cache maintenance pipeline" bit enabled...