• ARMv8 memory ordering
    In the ARM Architecture Reference Manual issue D.a (ARM DDI 0487D.a) section K11.3.1 "Acquiring a lock" has the following example code: AArch32 Px PLDW[R1] ; preload into cache in unique state Loop...
  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?
    Hi, I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores. The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters...
  • ARMv8: strongly ordered memory and exclusive access
    We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core. While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly...
  • CPUID information about ARMv8 core
    Hi experts, I want to know if there are CPUIDs information in CHI interface about IP A53/57 Mpcore? and can CCN504 transfer the CPUIDs to Slave device? for example, AXI_USER? Thanks.
  • ARMv8 EL1 MMU
    Hi,     I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1. I am not able to set sctlr_el1.M bit when ever i try to set this bit the...