• Why do we need atomicity in ARM Architecture?
    How does atomicity work with the memory accesses?
  • ARMv8.1-A: Access Flag managed by Hardware
    Hi ! I am currently using the Access Flag with software management, and I recently read about the v8.1 evolution with hardware management. From the reference manual: When the hardware management of...
  • ARMv8.1-A:How to disable the hardware management of the Access flag
    Hi ARM expert, I need do something when dealing with the access flag fault. But in ARMv8.1-A, there is an option of hardware management of the Access flag. Can anybody tell me how to set the option...
  • [Cortex-A53] STP instruction stores out of the specified memory
    Hi Experts, I have a question about "STP" instruction in Cortex-A53. STP W6, W6, [SP, #20] --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted. I don't know why cause it....
  • Atomic write (LDAXR/STLXR) causes infinite loop on Cortex-A72
    I have code which runs on Cortex-A72 (AArch64) and it disassembles to the following: 0: d53800a9 mrs x9, mpidr_el1 4: 92400529 and x9, x9, #0x3 8: b4000069 cbz x9, 0x14 c: d503205f wfe 10: 17ffffff...