• Arm64 Long Format Translation Table Walk
    Hi all - I'm trying to understand stage 1 translation. Assuming that the translation is starting at level 2, how do you determine the number of page table entries in the level 2 table? The documnetation...
  • Arm a53: Populate TLB without table walk?
    Hi, From a previous question I got that setting the EPDx bits from the TCR_ELx register to 1 will disable table walk. Good starting point. But, should I access the same memory location again, it won...
  • data cached during level-2 page walk
    Hello, Background : I am trying to trigger and mitigate L2 cache parity errors for a dual core Cortex A9 CPU integrated with an ARM PL310 L2 cache controller. Among the L2 cache parity errors, there...
  • page table Cachability bit effect!
    Hi experts, I really get confused with the page table cachability bit (c bit) effect (Cortex-A8) and need your help to find answer of my question. The questions is whether page table C-bit only controls...
  • Penalty estimate of TLB miss or table walk in armv8
    Hello! Is there are rough estimate oh what would be the penalty for each tlb miss or table walk for different table levels? And what are the factors that can determine the deviation between each measurement...