• Completing the set!
    You might have come across some pieces I've written recently on the ARMv7 architecture. Navigating the Cortex Maze ARMv7-A - Power to the People ARMv6-M vs ARMv7-M - Unpacking the Microcontrollers I've...
  • Is Cortex-A56 Maia or Artemis?
    I find an event "Real-Time & Embedded Computing Conference (RTECC)" from ARM official website. ARM will introduce The ARM Processor Roadmap Deciphered including Cortex-A56 (64-bit) in this event.  Considering...
  • What is the PMU counter resolution when the processor switches between 64-bit and 32-bit mode?
    Hi experts, The PMU counter value is mentioned as 64 bit in ARMV8 manual. What is the PMU counter resolution when the processor switches between 64 bit and 32 bit mode
  • Crypto in ARM v8
    Hi, ARM experts:   I found there are some crypto instructions in v8 Arch, they use register Vn.   Does these operations own a secure property,  i.e.  how to ensure non-secure world can not visit or dump...
  • Cortex-A53 Cache protection
    Hello all, The "Core Technical Reference Manual" specifies in chapter 8.2 the error reporting mechanism for all types of uncorrectable errors in the caches, except for L1 D-cache data (which is SEC...