• MMU initialization for an ARM multicore system
    I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib). On the shared SDRAM, I am planning to have dedicated...
  • Cortex A9 MMU
    Hello, I run a baremetal program on one core of the Cortex A9. The First Stage Bootloader (FSBL, Pre-Loader) and the Second Stage Bootloader (SSBL) perform perfectly. When the baremetal application...
  • Disabling the MMU
    Hello everybody! I am working on a IMX-6 and i have a little problem with the MMU. I want to write on some registers which are blocked by the MMU, so i want to disable it. I went on this page ARM Information...
  • ARMv8 EL1 MMU
    Hi,     I am working on bootloader porting to ARM v8 platform. I am facing a problem in enabling MMU in execution level-1 EL1. I am not able to set sctlr_el1.M bit when ever i try to set this bit the...
  • ARMv8-A:TrustZone and MMU
    I wonder how VA->PA translation is handled from non-secure world with Aarch64. I see the HYP mode uses IPA so that the second stage translation may restrict the VM to certain memory. But what about limiting...