• Significance of the WVALID signal in AXI
    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are...
  • AXI Write Access: WLAST/WVALID handling
    Can I set WLAST high while WVALID is low? The AXI specification is not clear at this point.
  • In AXI Interface, is the VALID signal of the master dependent on the slave's READY signal
    Hi, I am seeing an issue, where the READY signal's assertion depends on the VALID signal. If the VALID signal remains asserted through out the transaction (Say, for a burst transfer), then for the second...
  • AXI WR_STRB=0's when WVALID =1.
    In AXI, how does the slave interpret WR_STRB=0's when WVALID =1. Agreed it is not common for the master to generate it. Not sure if this is a bug or should my slave be smart enough to detect this case...
  • AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...