• ARM Cortex A8 L2 Cache Flush Invalidate
    Hi, I am working on DM37xevm platform and already invalidate the L2 cache (256KB) using the code asm volatile moveq r12, #0x1");                                                  asm volatile ("smc #1...
  • System wide cache flush
    Hello, I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system: My need is to flush a cached memory area to RAM in order to be viewed by the M4 core...
  • cache invalidation
    Hi, If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written...
  • ARM Cortex A9 flush cache
    I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements. Is it doable from user mode? Processor: ARM Cortex...
  • Clean and Invalidate Cache Memory
    Hi experts, Wat is the key difference between clean and invalidate the cache memory ? How it is related to eviction of data into the external memory ? What happens if any one of the operations alone carried...