• AXI3 data interleaving
    Hi, I was going through write data interleaving section in ARM AXI3 protocol. Found this statement: "For a slave that supports write data interleaving, the order in which it receives the first data item...
  • AXI3 & AXI4 wrap burst length
    Hi, Was going through AXI spec. As per AXI spec: "AXI3 supports burst lengths of 1 to 16 transfers, for all burst types." "AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers...
  • unaligned transfers
    Hi all i have some questions. Q1 if the master write a burst started in unaligned address. How to know the slave support unaligned transfers or not? Q2 AXI spec mention that the AXI protocol...
  • Does AMBA 4 ACE backward compatible with AXI3?
    Does AMBA 4 ACE backward compatible with AXI3? Suppose that I don't need all the coherency features
  • Cortex R8 axi unaligned transfer
    I have an issue in my retarget printf study AXI master port have not any transfer when I change address to unaligned address There is my C code volatitle int *tube = (volatile int *)0xfc000000;...