• Use of WVALID signal in AXI
    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are...
  • How should a AXI MASTER or SLAVE behave when a xREADY signal is never asserted?
    Hi all, I was trying to extract this information from the AXI specification but I didn't find any clear answer. I wonder how should an AXI component behave if an input xREADY signal is never asserted...
  • Significance of the WVALID signal in AXI
    In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are...
  • Difference in AxCACHE signal values in AXI protocol
    Hello, I am new to AXI. Where should I lookout for information on awcache signal. The protocol has various cache transfers. What is the difference between each of them? Where can I lookout for this...
  • Write interleaving with Multi-AXI master
    Hi, I have multiple questions related to multi-master AXI4 system. Eg: lets say we have 2 masters(m1,m2) and 2 slaves(s1,s2) and an interconnect. 1) In parallel, Can i have transfers(burst) to m1->s1...