• How to do cache invalid on Cortex-A53?
    hi,      I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.      Could you give me any suggestion about cache invalid? Thanks!     ...
  • Clean and Invalidate Cache Memory
    Hi experts, Wat is the key difference between clean and invalidate the cache memory ? How it is related to eviction of data into the external memory ? What happens if any one of the operations alone carried...
  • Need to invalidate L1 cache after DMA on Cortex A9
    Hi, I'm using a Renesas RZ/A1L, Cortex A9 microcontroller. After a DMA operation which transfers some data from a SPI module into RAM, I can't read the data correctly unless I've disabled L1 cache. (The...
  • Cache cleaning and invalidating in ARM Cortex-A
    Cleaning or invalidating the L1 cache and L2 cache will not be a single atomic operation. A core might therefore perform cache maintenance on a particular address in both L1 and L2 caches only as two...
  • CAT Cache Allocation Technology) and CDP (code and Data Prioritization) features support
    Hi, XEN 4.7 (last version of Hypervisor Xen) is supporting following cache features:   - CAT Cache Allocation Technology   - CDP Code and Data Prioritization Those features are supported by x86 L3 caches...