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  • MMU initialization for an ARM multicore system
    I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib). On the shared SDRAM, I am planning to have dedicated...
  • ARM Cortex-A9 | Non-cacheable memory range
    Note: This was originally posted on 23rd May 2013 at http://forums.arm.com Hi all, I am designing an application on xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using...
  • Which ARMv8 register controls cache partitioning
    Hi ARM folks, Which register controls the cache partitioning behavior on ARMv8 chips? My group is working with a Cavium ThunderX, and we're trying to experiment with different cache partitioning...
  • What is eXecute-Only-Memory (XOM)?
    An introduction to eXecute-only-Memory eXecute-Only-Memory (XOM) is a firmware protection technique to help prevent 3rd parties from stealing or reverse engineering firmware, and at the same time allowing...