• Cortex A15 SCU
    Hi, I find no introduction about SCU registers of A15 in the TRM. So, can software control SCU? Especially is SCU needed to be enabled by software? Thanks&Regards.
  • Cortex A9 SCU Control Register Enable bit 0 or 1 for enable changed in Manual from g to h?
    The Cortex-A9 MPCore Technical Reference Manual Revision: r4p1 describes the Bit 0 of scu-control-register as 0 SCU enable 1 SCU disable. (this is Version i of the manual) In Version g of the manual...
  • CORTEX-A processor interrupt handling
    Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation...
  • How to use the performance monitor of Cortex-A9?
    Hello experts, I feel I am an amateur. I tried to work the performance monitor of Cortex-A9 but it did not work. The followings are my codes. Please tell me what was wrong.         mov     r3, #0   ...
  • Cortex-A9 core registers
    In RTL code of A9mp platform provided by ARM, I see that almost all registers are renamed and are out of order(There are registers named R0-R55). This make it quite difficult for me to debug some problems...