• AMBA3 AXI - Exclusive access
    1/ What will happen when a master performs 2 exclusive read with 2 different transaction ID to the sam an address location?? Example: Master0 (M0) issue 2 exclusive read with 2 different transaction ID...
  • AMBA3 AXI - Exclusive access - 04/16/2015
    In document on AXI3: " The exclusive access monitor records the address and ARID value of any exclusive read operation. Then it monitors that location until either a write occurs to that location or until...
  • AXI Atomic Access
    Hello, I don't know whether this question has been asked or not. If yes please direct me to the appropriate discussion. My question is: 1. Suppose there are two masters, M0, M1 and one slave, S0. M0 initiates...
  • AXI problem
    Hi All I have few questions about axi Q1: is it possible that WVALID , WREADY and BVALID assert at the same cycle? Q2: what is different between out of order and data interleaving ? Q3: is it possible...
  • What's the relationship between exclusive access and memory cacheable in Cortex A53?
    Hello community and experts, I am doing an experiment on Cortex-A53 which executes some exclusive access instructions such as 'ldaxr'. When I config memory to Normal type+cacheable, 'ldaxr' can execute...