• ARMv7 CortexA9 Cache Policy - No allocate ?
    I was wondering if it would be possible to configure cache policy in the page table entry (short descriptor format) in such a way that the cache is used only if the data already exists in the cache? A...
  • Can Floating Point Unit(FPU) in cortexA9 processor raise an exception?
    Based on ARM documents there is no exception ID for FPU (CortexA9) and just FPU instructions set exception flags in Floating-Point Status and Control Register (FPSCR). Is there a way to use these flags...
  • Speculative data fetching on ARMv7-M
    I am working with an ARMv7-M with a cache and trying to workout how the Speculative data fetching works or at least understand it. The only documentation I can find for it is a small section in ARM...
  • instructions fetch
    Hello, when I use stm32f103xx, I am confused of one of the boot modes it supported. One of the boot modes is booting from embedded SRAM while the I-BUS of Cortex-M3 is connected to FLASH only . When boots...
  • If the mispredict happen, is there a mechanism to abort the instructions(have been fetched or decoded)?
    If the mispredict happen, is there a mechanism to abort the instructions(have been fetched or decoded)? If there is the mechanism, how does it work? Thanks very much!