• How to determine which core is generating the AXI read transaction in a multi core processor?
    I am currently working on Cortex A72 processor. I have generated hex file by compiling the c code file and asm file using Tizen compiler. The code consists of boot code for each core and each core starts...
  • WT it non cache able memory when it broadcast at transaction
    when we says "Cortex-A53 processor simplifies the coherency logic by downgrading memory to non Cache able if it is marked as Inner Write-Through or outer Write though" what is excatly this means ..Is...
  • Inconsistent shareability domain on tlbi instructions
    I'm using a IMX8QM system which features a dual-core A72 cluster plus a quad-core A53 cluster. Running on EL2 from one of the A53 cores I want to unmap a single page for all cores, so after I remove the...
  • Cortex-A72 and Cortex-A5x series boards
    Hi Experts, Is there any sample development boards available on Cortex-A72/5x series ? Regards, Techguyz
  • about cortex-A72
    hello guys, can you tell me the number of execution units in Cortex-A72 and the number of clock cycles it takes per instruction? Thanks in advance